This invention relates to semiconductor memory devices, and more particularly to a quasi-static read/write memory cell.
Semiconductor memory devices manufactured at the present time are for the most part of two types, static or dyamic. Static cells usually consist of bistable flip-flop circuits having six transistors, four transistors and two resistors as shown in U.S. Pat. No. 4,110,776, issued to G. R. Mohan Rao et al, assigned to Texas Instruments. Dyanamic cells are usually of the one-transistor type shown in pending application Ser. No. 648,594, filed Jan. 12, 1976, by C-K. Kuo, assigned to Texas Instruments. The static cells use too much power because one side of each latch is always conductive, and also require excessive space on the chip. The dyanmic cells are smaller and use little power, but the stored voltage leaks off the capacitor so periodic refresh is needed. The refresh operation uses part of the system operating time and also requires address counters and other circuitry to generate the refresh address and the like.
It is the principal object of this invention to provide an improved semiconductor memory cell. Another object is to provide a static type memory cell which does not have to be periodically addressed for refresh. A further object is to provide a memory cell which uses less power than static latch type cells and is smaller in size.